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Write 8086 ALP to interface DAC and generate following waveforms on oscilloscope, (i) Square wave

Aim: Write 8086 ALP to interface DAC and generate following waveforms on oscilloscope,

(i) Square wave - Variable Duty Cycle and Frequency.

(ii) Ramp wave - Variable direction,

(iii) Trapezoidal wave

(iv) Stair case wave

Apparatus: 8086 Kit, DAC 0808 Card, Interfacing Cables, CRO, SMPS.

Objective:

1. To understand the interfacing of DAC 0808 kit to 8086 kit,
2. To understand the operation of DAC 0808 to generate different waveforms.

Theory:

1. Performance parameters
1. Resolution: This is the number of possible output levels the DAC is designed to reproduce. This is usually stated as the number of bits it uses, which is the base two logarithm of the number of levels.
2. Maximum sampling rate: This is a measurement of the maximum speed at which the DACs circuitry can operate and still produce the correct output.
3. Monotonicity: This refers to the ability of a DAC's analog output to move only in the direction that the digital input moves
4. Settling time: settling time is the interval between a command to update (change) its output value and the instant it reaches its final value, within a specified percentage.
2. Different techniques of conversions:
1. Binary weighted resistor D/A converter

2. R/2R Ladder D/A converter,

3. Sources of errors in DAC:
1. Differential Nonlinearity error: DNL error is the difference between the ideal and the measured output responses for successive DAC codes. An ideal DAC response would have analog output values exactly one code (LSB) apart (DNL = 0).
2. Offset error: Offset error, often called 'zero-scale' error, indicates how well the actual transfer function matches the ideal transfer function at a single point. For an ideal data converter, the first transition occurs at 0.5LSB above zero. For a DAC, offset error is the analog output response to an input code of all zeros.
3. Gain error: indicates how well the slope of an actual transfer function matches the slope of the ideal transfer function. Gain error is usually expressed in LSB or as a percent of full-scale range (%FSR), and it can be calibrated out with hardware or in software. Gain error is the full-scale error minus the offset error.
4. Block Diagram of DAC 0808:

5. Pin Diagram & Features of DAC 0808

Pin Diagram

Features:

• Relative accuracy: ±0.19% error maximum
• Full scale current match: ±1 LSB typ
• Fast settling time: 150 ns typ
• Noninverting digital inputs are TTL and CMOS compatible
• High speed multiplying input slew rate: 8 mA/μs
• Power supply voltage range: ±4.5V to ±18V
• Low power consumption: 33 mW @ ±5V

Procedure:

1. Get machine codes for assembly language program to generate different analog waveforms.
2. Connect SMPS to DAC & 8086 kit.
3. Connect CRO to DAC.
4. Connect DAC card to 8086 kit using 26 pin FRC, through J2 (Used for U7- 8255 IC),
5. Enter machine codes to generate different waveforms and execute.
6. Observe the different waveforms on CRO,
7. Take readings for different parameters like Amplitude, Frequency, Duty cycle
8. Draw waveforms on graph paper.

Working of DAC Card:

1. We are using U7- 8255 IC to interface DAC kit,
2. Port A & B are used as output ports and port C as input port.
3. Port A is connected to DATA lines of DAC, PB0 is connected to ‘G’ pin of 74373 Latch IC, Port C is used to read status of DAC,
4. Initialise 8255 using control word (89 - to set PA,PB as output port, PC as input port and all ports in MODE 0)
5. Initialise 74373 Latch IC by making PB0 high i.e. by sending 01h to on port PB,
6. Execute the program to generate different waveforms,
7. Observe the waveform on CRO.
8. Take readings.

Algorithms for programs:

A) Algorithm for Square wave with Variable Duty Cycle and frequency:

1. Initialise U7- 8255 with CW 89h
2. Initialise 74373 Latch IC by sending 01h to PB,
3. Get 0FFh in AL register and send to DAC using PA,
4. Insert delay equal to ON time (Ton)
5. Get 00h in AL register and send to DAC using PB,
6. Insert delay equal to OFF time (Toff)
7. Repeat Steps from 3 to 6,

For variable Duty cycle:

              Change Ton & Toff without changing T (Ton+Toff)

For variable Frequency:

              Change T (Ton + Toff)

B) Algorithm for Ramp wave (Variable Direction) generation:

1. Initialise U7- 8255 with CW 89h
2. Initialise 74373 Latch IC by sending 01h to PB,
3. Get 00h in AL register
4. Send to DAC
5. Increment AL &
6. Repeat 4 & 5

For reverse direction:

1. Initialise U7- 8255 with CW 89h
2. Initialise 74373 Latch IC by sending 01h to PB,
3. Get 0FFh in AL register
4. Send to DAC
5. Decrement AL &
6. Repeat 4 & 5

C) Algorithm for Trapezoidal wave generation:

1. Initialise U7- 8255 with CW 89h,
2. Initialise 74373 Latch IC by sending 01h to PB,
3. Get 80h in AL register,
4. Send to DAC,
5. Increment AL & repeat till AL= FFh,
6. Insert delay ,
7. Decrement AL & Send to DAC till AL = 00h,
8. Insert delay,
9. Repeat from step 4.

D) Algorithm for Staircase wave generation:

1. Initialise U7- 8255 with CW 89h,
2. Initialise 74373 Latch IC by sending 01h to PB,
3. Initialise SI with 2000h
4. Initialise counter with 05h
5. Get Byte from lookup table and send to DAC,
6. Insert delay,
7. Increment SI
8. Decrement count & repeat step 5,6,7 & 8 till count get zero,
9. Initialise counter with 05h
10. Get byte from lookup table and send to DAC,
11. Insert delay,
12. Decrement SI
13. Decrement count & repeat step 10,11,12 & 13 till count get zero,
14. Repeat from step 3

Conclusion: Hence we have performed the practical to generate different waveforms using Dyna86 kit and DAC card.

Department of Computer Engineering

ALP Sheet for Microprocessor Interfacing Laboratory

Tiltle: Write 8086 ALP to interface DAC and generate following waveforms on oscilloscope,

(i) Square wave - Variable Duty Cycle and Frequency. (ii) Ramp wave - Variable direction,

(iii) Trapezoidal wave (iv) Stair case wave.

Assembly Language Program: Square Wave

Address (CS:IP)	Label	Instruction	Remark
0000:1000	START:	MOV AL,89	; Initialise 8255 (10001001B: Port A & B Output & Port-C input)
0000:1002		OUT 67,AL	; Send to control word
0000:1004		MOV AL,01	; Enable 74373 Latch by making PB0=1
0000:1006		OUT 63,AL	; Send to Port B
0000:1008	AGAIN:	MOV AL,FF	; ON CYCLE
0000:100A		OUT 61,AL	; Send to Port A
0000:100C		CALL DELAY	; Call delay routine from address 5000H
0000:100F		MOV AL,00	; OFF CYCLE
0000:1011		OUT 61,AL	; Send to Port A
0000:1013		CALL DELAY	; Call delay routine from address 5000H
0000:1016		JMP AGAIN	; Repeat
DELAY ROUTINE AT ADDRESS (0000:5000)
0000:5000	DELAY:	MOV CX,03FF	; Load Count to Create delay
0000:5003	SAME:	LOOP SAME	; Loop till CX becomes zero
0000:5005		RET	; Return

Assembly Language Program: Ramp Wave

Address (CS:IP)	Label	Instruction	Remark
Rising Ramp Wave
0000:2000	START:	MOV AL,89	; Initialise 8255 (10001001B: Port A & B Output & Port-C input)
0000:2002		OUT 67,AL	; Send to control word
0000:2004		MOV AL,01	; Enable 74373 Latch by making PB0=1
0000:2006		OUT 63,AL	; Send to Port B
0000:2008	AGAIN:	MOV AL,00	; Start from 00
0000:200A		OUT 61,AL	; Send to Port A
0000:200C		INC AL	; increment the digital input
0000:200E		JMP AGAIN	; Repeat
Falling Ramp Wave
0000:2500	START:	MOV AL,89	; Initialise 8255 (10001001B: Port A & B Output & Port-C input)
0000:2502		OUT 67,AL	; Send to control word
0000:2504		MOV AL,01	; Enable 74373 Latch by making PB0=1
0000:2506		OUT 63,AL	; Send to Port B
0000:2508	AGAIN:	MOV AL,FF	; Start from FF
0000:250A		OUT 61,AL	; Send to Port A
0000:250C		DEC AL	; Decrement the digital input
0000:250E		JMP AGAIN	; Repeat

Assembly Language Program: Trapezoidal Wave

Address (CS:IP)	Label	Instruction	Remark
0000:3000	START:	MOV AL,89	; Initialise 8255 (10001001B: Port A & B Output & Port-C input)
0000:3002		OUT 67,AL	; Send to control word
0000:3004		MOV AL,01	; Enable 74373 Latch by making PB0=1
0000:3006		OUT 63,AL	; Send to Port B
0000:3008		MOV AL,00	; Start from 00
0000:300A	UP1:	OUT 61,AL	; Send to Port A
0000:300C	AGAIN:	INC AL	; increment the digital input
0000:300E		CMP AL,FF	; Check for FF
0000:3010		JNE UP1	; If not equal go to UP1
0000:3012		OUT 61,AL	; Send to Port A
0000:3014		CALL DELAY	; Insert delay
0000:3017	UP2:	DEC AL	; Decrement the digital input
0000:3019		OUT 61,AL	; Send to Port A
0000:301B		CMP AL,00	; Check for 00
0000:301D		JNE UP2	; If not equal go to UP2
0000:301F		CALL DELAY	; Insert delay
0000:3022		JMP AGAIN	; Repeat

Assembly Language Program: Staircase Wave

Address (CS:IP)	Label	Instruction	Remark
0000:4000	START:	MOV AL,89	; Initialise 8255 (10001001B: Port A & B Output & Port-C input)
0000:4002		OUT 67,AL	; Send to control word
0000:4004		MOV AL,01	; Enable 74373 Latch by making PB0=1
0000:4006		OUT 63,AL	; Send to Port B
0000:4008	BACK:	MOV CL,05	; Number of steps
0000:400A		MOV SI,4500	; Address of Array containing step value
0000:400D	UP1:	MOV AL,[SI]	; RISING STAIRCASE
0000:400F		OUT 61,AL	; Send to Port A
0000:4011		CALL DELAY	; CALL DELAY ROUTINE
0000:4014		INC SI	; Increment SI
0000:4016		DEC CL	; Decrement CL
0000:4018		JNZ UP1	; Jump if not zero to UP1
0000:401A		MOV CL,05	; Number of steps
0000:401C	UP2:	DEC SI	; Decrement SI
0000:401D		MOV AL,[SI]	; FALLING STAIRCASE
0000:401F		OUT 61,AL	; Send to Port A
0000:4021		CALL DELAY	; CALL DELAY ROUTINE
0000:4024		DEC CL	; Decrement CL
0000:4026		JNZ UP2	; Jump if not zero to UP2
0000:4028		JMP BACK	; Repeat
Array Containing Step Values
Address	Hex Value
0000:4500	00
0000:4501	40
0000:4502	80
0000:4503	C0
0000:4504	FF